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| GALVANTECH, INC. ASYNCHRONOUS SRAM FEATURES * * * * * * * * GVT72024A8 TRADITIONAL PINOUT 128K X 8 SRAM 128K x 8 SRAM WITH TWO CHIP ENABLE TRADITIONAL PINOUT GENERAL DESCRIPTION The GVT72024A8 is organized as a 131,072 x 8 SRAM using a four-transistor memory cell with a high performance, silicon gate, low-power CMOS process. Galvantech SRAMs are fabricated using double-layer polysilicon, double-layer metal technology. Static design eliminates the need for external clocks or timing strobes. For increased system flexibility and eliminating bus contention problems, this device offers two chip enables (CE1# and CE2) along with output enable (OE#) for this organization. The chip is enabled when CE1# is LOW and CE2 is HIGH. With chip being enabled, writing to this device is accomplished when write enable (WE#) is LOW and reading is accomplished when (OE#) go LOW with (WE#) remaining HIGH. The device offers a low power standby mode when chip is not selected. This allows system designers to meet low standby power requirements. PIN ASSIGNMENT 32-Pin SOJ NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Fast access times: 10, 12, 15and 20ns Fast OE# access times: 5, 6, 7 and 8ns Single +5V +10% power supply Fully static -- no clock or timing strobes necessary All inputs and outputs are TTL-compatible Three state outputs Easy memory expansion with CE1#, CE2 and OE# options High-performance, low-power consumption, CMOS double-poly, double-metal process OPTIONS * Timing 10ns access 12ns access 15ns access 20ns access Packages 32-pin SOJ (400 mil) 32-pin SOJ (300 mil) 32-pin TSOP (type I) Power consumption Standard Low Temperature Commercial Industrial MARKING -10 -12 -15 -20 * J SJ TS * None L * None I (0C to 70C) (-40C to 85C) VCC A15 CE2 WE# A13 A8 A9 A11 OE# A10 CE1# DQ8 DQ7 DQ6 DQ5 DQ4 PIN ASSIGNMENT 32-Pin TSOP (Type I) A11 A9 A8 A13 WE# CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE# A10 CE1# DQ8 DQ7 DQ6 DQ5 DQ4 VSS DQ3 DQ2 DQ1 A0 A1 A2 A3 Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051 Tel (408) 566-0688 Fax (408) 566-0699 Rev. 2/98 Galvantech, Inc. reserves the right to change products or specifications without notice. GALVANTECH, INC. FUNCTIONAL BLOCK DIAGRAM GVT72024A8 TRADITIONAL PINOUT 128K X 8 SRAM VCC VSS A0 DQ1 ROW DECODER ADDRESS BUFFER MEMORY ARRAY 512 ROWS X 256 X 8 COLUMNS I/O CONTROL DQ8 CE2 CE1# WE# OE# A16 COLUMN DECODER TRUTH TABLE MODE READ WRITE OUTPUT DISABLE STANDBY STANDBY CE1# L L L H X CE2 H H H X L WE# H L H X X OE# L X H X X DQ Q D HIGH-Z HIGH-Z HIGH-Z POWER ACTIVE ACTIVE ACTIVE STANDBY STANDBY POWER DOWN PIN DESCRIPTIONS SOJ & DIP Pin Numbers TSOP Pin Numbers SYMBOL A0-A16 TYPE Input DESCRIPTION Addresses Inputs: These inputs determine which cell is addressed. 12, 11, 10, 9, 8, 7, 20, 19, 18, 17, 16, 6, 5, 27, 28, 23, 15, 14, 13, 3, 2, 31, 25, 4, 28, 3, 31, 2 1, 12, 4, 11, 7, 10 29 22, 30 5 30, 6 WE# CE1#, CE2 Input Write Enable: This input determines if the cycle is a READ or WRITE cycle. WE# is LOW for a WRITE cycle and HIGH for a READ cycle. Chip Enables: These inputs are used to enable the device. When CE1# is LOW and CE2 is HIGH, the chip is selected. When either CE1# is HIGH or CE2 is LOW, the chip is disabled and automatically goes into standby power mode. Output Enable: This active LOW input enables the output drivers. SRAM Data I/O: Data inputs and data outputs Input 24 13, 14, 15, 17, 18, 19, 20, 21 32 16 32 21, 22, 23, 25, 26, 27, 28, 29 8 24 OE# DQ1-DQ8 VCC VSS Input Input/ Output Supply Power Supply: 5V +10% Supply Ground February 5, 1998 2 Galvantech, Inc. reserves the right to change products or specifications without notice. Rev. 2/98 GALVANTECH, INC. ABSOLUTE MAXIMUM RATINGS* GVT72024A8 TRADITIONAL PINOUT 128K X 8 SRAM *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on VCC Supply Relative to VSS........-0.5V to +7.0V VIN ..........................................................-0.5V to VCC+0.5V Storage Temperature (plastic) ..........................-55oC to +125o Junction Temperature .....................................................+125o Power Dissipation ...........................................................1.2W Short Circuit Output Current .......................................50mA DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (All Temperature Ranges; VCC = 5V +10% unless otherwise noted) DESCRIPTION Input High (Logic 1) voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage 0V < VIN < VCC Output(s) disabled, 0V < VOUT < VCC IOH = -4.0mA IOL = 8.0mA CONDITIONS SYMBOL VIH VIl ILI ILO VOH VOL VCC MIN 2.2 -0.5 -5 -5 2.4 MAX VCC+1 0.8 5 5 UNITS V V uA uA V NOTES 1, 2 1, 2 1 1 1 0.4 4.5 5.5 V V DESCRIPTION Power Supply Current: Operating TTL Standby CMOS Standby CONDITIONS Device selected; CE1# < VIL & CE2 > VIH; VCC =MAX; f=fMAX; outputs open CE1# >VIH or CE2 SYM Icc ISB1 ISB2 TYP 80 20 0.02 POWER -10 210 200 60 45 5 0.4 -12 180 170 55 40 5 0.4 -15 150 140 50 35 5 0.4 -20 110 110 40 30 5 0.4 UNITS NOTES mA mA mA 3, 14 14 14 standard low standard low standard low CAPACITANCE DESCRIPTION Input Capacitance Input/Output Capacitance (DQ) CONDITIONS TA = 25oC; f = 1 MHz VCC = 5V SYMBOL CI CI/O MAX 6 8 UNITS pF pF NOTES 4 4 February 5, 1998 3 Galvantech, Inc. reserves the right to change products or specifications without notice. Rev. 2/98 GALVANTECH, INC. AC ELECTRICAL CHARACTERISTICS (Note 5) (All Temperature Ranges; VCC = 5V DESCRIPTION READ Cycle READ cycle time Address access time Chip Enable access time Output hold from address change Chip Enable to output in Low-Z Chip disable to output in High-Z Output Enable access time Output Enable to output in Low-Z Output Enable to output in High-Z Chip Enable to power-up time Chip disable to power-down time WRITE Cycle WRITE cycle time Chip Enable to end of write Address valid to end of write, with OE# HIGH Address setup time Address hold from end of write WRITE pulse width WRITE pulse width, with OE# HIGH Data setup time Data hold time Write disable to output in Low-Z Write Enable to output in High-Z tWC tCW tAW tAS tAH tWP2 tWP1 tDS tDH tLZWE tHZWE tRC tAA tACE tOH tLZCE tHZCE tAOE tLZOE tHZOE tPU tPD GVT72024A8 TRADITIONAL PINOUT 128K X 8 SRAM +10%) - 10 - 12 MIN MAX - 15 MIN MAX - 20 MIN MAN UNITS NOTES SYM MIN MAX 10 10 10 3 3 5 5 0 5 0 10 10 8 8 0 0 10 8 6 0 3 5 12 12 12 4 4 6 6 0 6 0 12 12 8 8 0 0 10 8 6 0 4 6 15 15 15 4 4 7 7 0 7 0 15 15 9 9 0 0 11 9 7 0 5 7 20 20 20 4 4 8 8 0 8 0 20 20 10 10 0 0 12 10 8 0 5 8 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4, 7 4, 6, 7 4, 6 4 4 4, 7 4, 6, 7 February 5, 1998 4 Galvantech, Inc. reserves the right to change products or specifications without notice. Rev. 2/98 GALVANTECH, INC. AC TEST CONDITIONS Input pulse levels Input rise and fall times Input timing reference levels Output reference levels Output load 0V to 3.0V 1.5ns 1.5V 1.5V See Figures 1 and 2 GVT72024A8 TRADITIONAL PINOUT 128K X 8 SRAM OUTPUT LOADS Q Z 0 = 50 50 Vt = 1.5V Fig. 1 OUTPUT LOAD EQUIVALENT +5V 480 Q 255 5 pF 30 pF Fig. 2 OUTPUT LOAD EQUIVALENT NOTES 1. 2. 3. 4. 5. 6. 7. All voltages referenced to VSS (GND). Overshoot: Undershoot: VIH +7.0V for t tRC /2. VIL -2.0V for t tRC /2 8. 9. WE# is HIGH for READ cycle. Device is continuously selected. Chip enable and output enables are held in their active state. Icc is given with no output current. Icc increases with greater output loading and faster cycle times. This parameter is sampled. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. Output loading is specified with CL=5pF as in Fig. 2. Transition is measured +500mV from steady state voltage. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE. 10. Address valid prior to, or coincident with, latest occurring chip enable. 11. tRC = Read Cycle Time. 12. Chip Enable and Write Enable can initiate and terminate a WRITE cycle. 13. Capacitance derating applies to capacitance different from the load capacitance shown in Fig. 1. 14. Typical values are measured at 5V, 25oC and 20ns cycle time. DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only) DESCRIPTION Vcc for Retention Data Data Retention Current CE1# >VCC -0.2 or CE2< VSS +0.2; all other inputs < VSS +0.2 or >VCC -0.2; all inputs static; f= 0 Vcc = 2V Vcc = 3V CONDITIONS SYMBOL MIN 2 TYP MAX UNITS V NOTES VDR ICCDR ICCDR 2 3 100 150 uA uA 13 13 Chip Deselect to Data Retention Time Operation Recovery Time tCDR tR 0 ns ns 4 4, 11 tRC February 5, 1998 5 Galvantech, Inc. reserves the right to change products or specifications without notice. Rev. 2/98 GALVANTECH, INC. GVT72024A8 TRADITIONAL PINOUT 128K X 8 SRAM LOW VCC DATA RETENTION WAVEFORM DATA RETENTION MODE DATA RETENTION MODE VCC VIH VIL VIH VIL 4.5V tCDR VDR 4.5V tRC CE1# CE2 < 0.2V READ CYCLE NO. 1(8, 9) t RC ADDR t AA t OH VALID Q PREVIOUS DATA VALID READ CYCLE NO. 2(7, 8, 10, 12) tRC DATA VALID CE1# CE2 tAOE tLZOE OE# tACE tLZCE tHZCE tHZOE Q HIGH Z DATA VALID DON'T CARE UNDEFINED February 5, 1998 6 Galvantech, Inc. reserves the right to change products or specifications without notice. Rev. 2/98 GALVANTECH, INC. GVT72024A8 TRADITIONAL PINOUT 128K X 8 SRAM WRITE CYCLE NO. 1(7, 12, 13) (Write Enable Controlled with Output Enable OE# active LOW)) t WC ADDR t AW t t AH CW CE2 CE1# t AS t WP2 WE# t DS t DH D t DATA VALID HZWE t LZWE Q HIGH Z WRITE CYCLE NO. 2(12, 13) (Write Enable Controlled with Output Enable OE# inactive HIGH) t WC ADDR tAW t t AH CW CE2 CE1# tAS tWP1 WE# tDS tDH D Q DATA VALID HIGH Z DON'T CARE UNDEFINED February 5, 1998 7 Galvantech, Inc. reserves the right to change products or specifications without notice. Rev. 2/98 GALVANTECH, INC. GVT72024A8 TRADITIONAL PINOUT 128K X 8 SRAM WRITE CYCLE NO. 3(12, 13) (Chip Enable Controlled) t WC ADDR tAW tAS t tAH CW CE2 CE1# tWP1 WE# tDS tDH D DATA VALID HIGH Z Q DON'T CARE February 5, 1998 8 Galvantech, Inc. reserves the right to change products or specifications without notice. Rev. 2/98 GALVANTECH, INC. Package Dimensions GVT72024A8 TRADITIONAL PINOUT 128K X 8 SRAM 32-pin 400 Mil Plastic SOJ (J) .830 (21.08) .820 (20.83) .405 (10.29) .395 (10.03) .445 (11.30) .435 (11.05) PIN #1 INDEX .050 (1.27) TYP .145 (3.68) .131 (3.33) SEATING PLANE .020 (0.51) .015 (0.38) .095 (2.41) .080 (2.03) .380 (9.65) .360 (9.14) .030 (0.76) MIN Note: All dimensions in inches (millimeters) MAX MIN or typical, min where noted. 32-pin 300 Mil Plastic SOJ (SJ) .825 (20.96) .810 (20.57) .305 (7.75) .292 (7.42) .340 (8.64) .330 (8.38) PIN #1 INDEX .050 (1.27) TYP .140 (3.55) .120 (3.04) SEATING PLANE .020 (0.51) .015 (0.38) .095 (2.41) .080 (2.03) .274 (6.95) .254 (6.44) .025 (0.63) MIN Note: All dimensions in inches (millimeters) MAX MIN or typical, min where noted. February 5, 1998 9 Galvantech, Inc. reserves the right to change products or specifications without notice. Rev. 2/98 GALVANTECH, INC. Package Dimensions (continued) GVT72024A8 TRADITIONAL PINOUT 128K X 8 SRAM 32-pin Plastic TSOP (TS) .795 (20.20) .780 (19.80) .012 (0.30) .006 (0.15) .020 (0.50) TYP .319 (8.10) .311 (7.90) .047 (1.20) MAX .728 (18.50) .720 (18.30) .041 (1.05) .037 (0.95) Note: All dimensions in inches (millimeters) MAX MIN or typical, max where noted. Ordering Information GVT 72024A8 XX - XX X X Galvantech Prefix Part Number Temperature (Blank = Commercial I = Industrial) Power (Blank= Standard, L= Low Power) Speed (10 = 10ns, 12= 12ns, 15 = 15ns, 20 = 20ns) Package (J = 400 mil SOJ, SJ= 300 mil SOJ, TS= TSOP TYPE I) February 5, 1998 10 Galvantech, Inc. reserves the right to change products or specifications without notice. Rev. 2/98 |
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